Raspberry Pi Pico & RP2040

Features two processing cores running in parallel. This allows you to delegate time-critical tasks or communication loops to Core 1 while Core 0 handles the main loop without interruption.

A hardware subsystem unique to RP2040. Write cycle-perfect assembly to emulate custom hardware interfaces (DVI, VGA, SD cards) without placing any execution load on the main CPUs.

Equipped with 264KB of high-speed SRAM divided into 6 independent banks. This unique matrix lets both cores and DMA channels access memory concurrently without bus contention.

Uses a high-efficiency on-board SMPS regulator allowing the board to operate from a wide range of power sources. Perfect for portable projects running on AA, AAA, or LiPo batteries.

Write expressive, high-level Python code instantly. Ideal for rapid prototyping, reading sensors, and controlling outputs without waiting for C++ compiler cycles.

Unlock the absolute maximum speed of the board. The comprehensive C/C++ SDK gives you register-level hardware control, raw clock scaling, and direct DMA register access.

Digital GPIO Pins

Ultra-flexible design: all 26 I/O pins can carry digital inputs/outputs and include internal pull-up and pull-down configurations.

• Supports 16 independent PWM outputs
• Highly customizable drive strength (2mA to 12mA)
• Fast toggle speed: directly accessible by PIO

Analog inputs (ADC)

Features 3 dedicated 12-bit ADC input channels (GP26, GP27, and GP28) converting analog readings up to 3.3V reference.

• Converts voltages into values from 0 to 4095
• Additional internal channel measures board temperature
• Capable of ultra-fast 500ksps sampling rate

Interface Multiplexing

Pins are heavily multiplexed, allowing dual UART, I2C, and SPI configurations to be routed to different pins depending on your wiring needs.

• Configure multiple independent communication lines
• Avoid physical routing conflicts easily
• PIO co-processors can drive additional buses

I2C Bus

2 Controllers (Flexible GP Routing)

Configure up to two independent I2C buses. Pins can be mapped dynamically across almost any digital GPIOs to avoid routing conflicts.

SPI Interface

2 Controllers (Up to 62.5 Mbps)

Two high-speed SPI interfaces supporting master/slave modes, perfect for driving color LCD displays and SD card modules.

UART Serial

2 Controllers (Up to 921.6 Kbps)

Dual hardware UART channels for robust serial terminal logging, GPS module interfacing, or ESP8266 AT command pipelines.

USB 1.1 controller

Host & Device Emulation

On-chip USB controller supporting Host and Device modes, allowing the Pico to natively act as a keyboard, mouse, or disk drive.

PIO Protocol Emulation

Cycle-Perfect Custom protocols

Emulate custom buses like I2S audio, WS2812B NeoPixel streams, CAN bus, or standard VGA outputs without loading the main CPU.

DMA Peripheral Control

Direct Memory Access Transfer

Offload data transfers between communication peripherals and memory buffers to background DMA channels.

Leverage both Cortex-M0+ cores. Run separate execution routines on each core, synchronizing them with low-latency hardware FIFO mailboxes.

Best practice: Core 1 handles interrupts, while Core 0 executes heavy algorithms.

Configure DMA channels to read or write directly to registers or memory space. Frees up processing overhead during screen drawing or sensor logging.

Application: Feed the DAC or SPI TFT framebuffers without CPU intervention.

Write cycle-accurate PIO assembly to shift data pins at precise speeds up to the system clock frequency.

Use case: Create extra custom UART, WS2812B, or high-speed hardware drivers.

Reduce the system clock down to 32.768kHz or power off the system PLL entirely to lower the current draw into microamps.

Pro tip: Program the built-in RTC (Real-Time Clock) to wake up the system.

The bootloader is hardwired directly into the silicon (BOOTROM), making it virtually impossible to break or brick the device.

No drivers needed: Pico mounts instantly as a standard flash drive on any OS.

SRAM memory is divided into 4 striped banks (64KB each) and 2 small scratchpad banks (4KB each).

Zero Contention: Cores and DMA can fetch data simultaneously from separate banks.

🐍 MicroPython: Blinking the LED

⚙️ C++ SDK: Blinking the LED