🔬 Verification & Design · 17 Chapters · 86 Lessons

SystemVerilog Engineering Guide

Master modern functional verification and hardware design. Aligned with the Hardware Verification Roadmap and VLSI Engineering Path.

1

1. Digital Design Fundamentals

Number Systems→Logic Gates→Combinational Logic→Sequential Logic→

2

2. Verilog Fundamentals

Verilog Basics→Data Types→Operators→Procedural Blocks→Behavioral Modeling→Structural Modeling→RTL Design→

3

3. SystemVerilog Fundamentals

Introduction→Logic Data Types→Arrays→Enumerations→Structures→Unions→Typedefs→

4

4. Procedural Programming Features

Tasks→Functions→Control Statements→Process Control (fork/join)→

5

5. Advanced Data Structures

Dynamic Arrays→Queues→Associative Arrays→Array Methods→

6

6. Object-Oriented Programming

Classes→Members→Encapsulation→Inheritance→Polymorphism→Abstract Classes→Packages→

7

7. Randomization

Random Variables (rand vs. randc)→Basic Constraints→Advanced Constraints→Randomization Methods & Controls→

8

8. Interprocess Communication

Mailboxes→Semaphores→Events→

9

9. Interfaces

Interfaces→Modports→Clocking Blocks→Virtual Interfaces→

10

10. Assertions (SVA)

Immediate vs. Concurrent Assertions→Temporal Operators→Sequences→Properties→Applications→

11

11. Functional Coverage

Covergroups→Coverpoints→Bins→Cross Coverage→Coverage Options→

12

12. Verification-Oriented SystemVerilog

Testbench Architecture→Transaction Level Modeling (TLM)→Reference Models→Checkers→

13

13. Concurrency and Scheduling

Scheduler Event Regions→Race Conditions & Prevention→Simulation Semantics→

14

14. Design-Oriented SystemVerilog

always_comb→always_ff→always_latch→Parameterized Designs→Generate Blocks→

15

15. Advanced Verification Concepts

Transaction Modeling→Factory Concepts→Callbacks→Configuration Techniques→

16

16. UVM Preparation

UVM Fundamentals→Phases→TLM→Sequences→Agents→Environment→

17

17. Expert-Level Topics

RTL Design→CDC (Clock Domain Crossing)→RDC (Reset Domain Crossing)→Formal Verification→AMBA AXI→AMBA AHB→AMBA APB→Low Power Verification→FPGA Design→ASIC Design Flow→

Ready for functional verification?

Begin with Lesson 1 to master SystemVerilog data types, logic vs wire, 2-state vs 4-state simulation, and testbench architecture.

Start Lesson 1: Number Systems →