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VLSI & ASIC Design
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Design physical silicon layouts from digital logic and SystemVerilog RTL through logic synthesis, floorplanning, placement, physical routing, and STA timing closure.
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Phase 1: RTL Hardware Description (SystemVerilog)
SystemVerilog/Verilog RTL Design
Write synthesisable hardware description modules using structured Verilog/SystemVerilog RTL blocks.
Phase 2: Logic Synthesis & Design Constraints
Logic Translation & SDC Timing Constraints
Translate SystemVerilog RTL code into technology-specific gate-level netlists.
Phase 3: Design for Testability (DFT)
Scan Insertion & Fault Coverage
Embed structural design-for-test architectures into the silicon chip to detect manufacturing faults.
Phase 4: Physical Design (PnR Layout)
Floorplanning, Placement & Physical Routing
Map gate netlists onto concrete 2D physical silicon die layouts.
Phase 5: Static Timing Analysis & Sign-off
STA Timing Checks & Silicon Sign-off
Verify the physical layout meets all strict setup, hold, and DRC rules across all PVT corners.